Working with Qsys by Professor Tim Johnson, 8/12/2013, revised 3/4/2014
Basically instead of starting SOPC Builder we pull down on Tools in the main menu and click on Qsys as seen below in figure 1.
Figure 1 Starting Qsys
Figure 2 Indication that Qsys software is starting up.
Figure 3 Opening screen for Qsys
The good news is there are no errors or warnings at this point (lower left corner). We’re going to install the same components as in the SOPC wizard. These are selected from the library on the left.
Figure 4 Open up Embedded Processors, select Nios II Processor, then click Add.
Figure 5 Opening screen of Nios II processor wizard. The web edition only allows us to use Nios II/e.
At this point, the setting and clearing the errors will be dealt with just like in the SOPC Builder so follow along in Lab 1 for those explanations clicking on the tabs along the top of the wizard above the Nios II selection guide choices. Select the Nios II/e core then the JTAG Level 1 and then click finish; errors will be dealt with after the on-chip memory is selected.
Figure 6 We picked up 2 more errors which will be dealt with later.
Figure 7 Nearly the same spot as the SOPC Builder had it.
Figure 8 Go with the defaults for the memory.
We picked up two more errors and a warning. Hmmm, SOPC Builder was much easier…
Figure 9 Results of adding the on-chip memory.
Figure 10 Our errors up to now. Qsys—a real confidence builder.
Now let’s clear some errors.
Figure 11 Click on nios2_qsys_0 to re-open the processor wizard.
Figure 12 Slide down until you see the Reset and Exception Vector and change them to Absolute.
Next we can start adding some I/0 connections; specifically the parallel I/O called PIO by Quartus.
Figure 13 Location of the PIO.
Figure 14 Make this bus an output, 8 bits, check off Enable individual bit…, then click Add.
Figure 15 Qsys up to this p
Let’s change the name of the PIO by right-clicking on the name and selecting rename to add “out_pio_0”. You can’t see the underscores when you are editing the name but they have to be there.
Figure 16 Right-click on this peripheral to bring up the selections.
Add a second PIO same size only with 4 bits input (won’t need an output register). Rename it to “in_pio_0”.
Both of these PIOs need the external connection from the Qsys to the pin outs we’ve place on the upper level architecture. In the Export column double click on the faded wording to change to:
Figure 17 State of the processor design at this point. All the I/O’s have been “connected” at this point.
The I/O’s consist of the clk, reset, pio_out, and pio_in as seen in the Export column. The reset will be connected to vcc and the rest will go to their pins on the upper level block diagram once the Qsys is inserted into the design.
Let’s add the JTAG I/O feature which is different than the JTAG function portion of the processor. The JTAG interface is how the programming instruction get from the computer to the actual chip and this terminology has remained constant in the industry for the last 30-40 years. Physically, it connects the programming USB cable through the board wiring to the chip. It passes through the hardware that lights the LEDs up to advise us when the programming is taking place by lighting up the programming LED.
Figure 18 The JTAG serial interface is located here.
Figure 19 Qsys with JTAG in place.
While were here at the JTAG it operates using an Interrupt. We need to connect it, see Figure 20. When you click on the connection it will change to the number 0 in a small box.
Figure 200 Side the view over to the right and click on the connection circled in red above.
We have a number of errors at this point. Some of them are clocking errors (5), some are reset errors (5), and five warnings are missing connection to the Avalon Memory Mapped Master in the Nios II processor core. The processor core has two MM Masters: one for Instructions and the other for Data. The clocks, the resets and the memory masters all have busses running down the length of the processor in the Connections column. Technically this is the magic of the SOPC and it is called Avalon fabric. So clearing the errors and warnings now becomes a game of who needs clocks, resets, and instructions/data or both.
What I would like you to do is make all the connections. You will be creating errors while you do that but that is because of memory location are overlapping which can be corrected later. Make your design should look like Figure 21:
Figure 211 Connecting the MM master busses to the modules.
All the missing connections are now replace with memory overlaps (14 on my machine). These can be viewed in the Messages Description or in the Address Map tab.
Figure 222 Address Map showing all the overlaps.
There used to be a real easy way to fix this in the SOPC Builder…one click and the program adjusted everything using an auto_assign_base_address command. Qsys has made the connections much more customizable but has increased the complexity. It turns out there is an assign_base_address command:
Figure 23 location of the auto adjust for base addresses.
Anyway, you can easily see that the data memory locations are the same as the instruction memory locations. I’m sure you can’t mix instructions with data and some modules may not even need instructions as they just pass data through. For instance, I was able to find out that the JTAG UART component doesn’t need a data connection, only instructions so I deselected the data connection but the JTAG module needs the connects to both data and instructions MM masters.
Figure 24 I call that button “Error be gone”.
Figure 25 Info Messages are just that INFORMATION which we can ignore (sometimes).
Figure 26 Final Challenge: adding the System ID
When you click Add, the options for the peripheral require some number for the ID. Write anything in; I kept it simple and set it to one. Some errors come up, so view the figure below to see how I cleared them:
Figure 27 Four connections were made.
The system is now ready to be generated. Move to the Generate Tab, change Synthesis to VHDL and check off Create block symbol file then click Generate and sit back and see what happens.
Figure 28 Setting for the Generate phase of the design.
I was required to save the file so I selected Lab1_demo_qsys because I remembered that *.bsf files don’t like being name the same as the project…all kinds of problems when you name the block symbol file the same as the project.
Figure 29 Love to see these kinds of results at the end.
Close out of the Generate report then X out of Qsys. Returning to the top-level design click on
the Symbol tool
Figure 30 Custom designed Nios II processor ready to insert into your project.
A final look at the Qsys design: