Connecting External Memory to NIOS II processor on the DE2
Author: Wilking Interiano
Objective: Tutorial detailing how to add 8 MB of SDRAM to Nios Processor. To understand more about SDRAM read the datasheet from Altera.
Pre-requisite: It is assumed you have completed Elec667 Lab 4 7-segment display to complete this lab.
Your SOPC must have the following components before beginning this lab (See Figure 1):
1.) Nios II Processor
2.) 8 bit parallel output called led_pio
3.) 16 bit parallel output called seven_seg_pio
4.) JTAG serial Interface
5.) System ID for debugging
6.) System Interval Timer sys_clk_timer
7.) On-chip memory
Part I: Add SDRAM controller in SOPC Builder
1.) Open your Quartus project which was used in Lab 4.
2.) Open the SOPC Builder by going to Tools -> SOPC Builder
SDRAM to System Control by going to the System Contents Tab > Memories and
Memory Controllers > External Memory Interfaces > SDRAM Interfaces >
Figure 2 Adding a SDRAM controller
are different settings to control SDRAM depending the
chip model available. We want to create a generic 8 MB chip in the SDRAM
controller wizard, change Presets to
Custom and Bits to 16. Then
5.) Leave timing to default settings and click Finish.
Figure 5 Final page of Wizard
6.) Modifiy the cpu reset and exception vectors to use SDRAM memory.
Figure 6 Setting for Reset and exception vectors.
7.) Auto assign memory addresses, System > Assign Base Addresses
Generate to update SOPC
Part II: Adding SDRAM to Block Diagram
processor must be updated by deleting the original processor in the block
diagram and add the update processor
Note: The name of the processor will not be count, but the name given in the SOPC builder
2.) Add the following pins to the block diagram and connect them to the appropriate signals.
NOTE: At this point the connections
that control SDRAM for read/write operation is set, however there is no clock
to actually run the SDRAM chip. In order to use SDRAM successfully, it must run
off a clock that is 3 ns slower than master clock driving the processor. If
SDRAM_CLK is not created or is connected to the same clock as the processor
then NIOS will run into run-time errors.
3.) A “slow clock” will be created to drive SDRAM. Click on Tools -> MegaWizard Plug-In Manager and click Next
4.) Choose pll to slow down master clock by going to Installed Plug-ins -> I/O -> ALTPLL
5.) Name the output file sdram_pll and click Next
6.) Change the frequency of the inclk0 input to 50.000 MHz and click Next.
7.) Make all the checkboxes are empty. Click Next
8.) Leave default settings for Clock switchover page and click Next
the following to C0 Clock Tap Settings
- Use Enter output clock frequency
10.) - Set Clock Phase Shift to -3 ns
10.) Click Next until Summary page is reached. Make sure Quartus II Symbol File is checked and click Finish
Add the sdram_pll to the block diagram. The input will be the master clock and the
output will connect to the SDRAM_CLK output.
The figure below is an example of what the final connections should look like.
Add the following assignments. Project
may have to be compiled in order for the nodes to appear in the pin planner.
13.) Compile the project again after the pin assignments are made.
Part III: Create Binary Count in Nios II IDE
1.) Open Nios II IDE
2.) Create a new Nios II Application and BSP from Template
3.) Add the Count Binary example and .sopcinfo from the previous section. Name the project countBinary.
4.) Right click the countBinary Project and Run as Hardware. This will build and execute the example code.
If the SOPC was built correctly,
and all the I/O connections made in Quartus with the proper assignments then
the example code should run successfully. The code demonstration on the board
runs identically as it did in Lab 4. The green LEDs should be counting up to
255 in binary, and the seven segment display should count up to FF.
The difference lies in the memory that the processor is using to run the example code, which is now using 8 MB of SDRAM. The example code requires 69 kB of memory, however, the FPGA on chip memory is limited to ~50 kB and only 20 kB was allocated in earlier labs. With more memory added, the processor is able to run the LCD if it was added in Quartus.