Wentworth Institute of Technology

Department of Electrical Engineering and Technology

Elec 667 Advanced Programmable Logic

Binary Count with LCD

 

Objective: Students implement the LCD display feature provided in the binary count template using SDRAM memory.

 

Reference Text: DE2 User Manual

 

Materials: DE2 Evaluation Board

 

Instructions:

  1. Begin a new project naming it Lab6 with its own folder under the Altera folder on the C drive. Build an entirely new SOPC for this lab.Below is the SOPC that was used in Lab 4.

 

Figure 1 Lab 4 SOPC design

2.       Weíre ready to work on adding the LCD screen output.Select the character LCD in Peripherals.

Figure 2 Character LCD is added to the design seen above as lcd_0

3.       Donít forget to change the name of the lcd_0 to lcd_display to match the code in the sample software Count_Binary.Now if we were to generate this SOPC we would see the following changes automatically implemented in the Lab4_processor design:

Figure 3 After generating the SOPC with the LCD display added.

4.       Did you notice we didnít have to add a parallel bus (pio) to the SOPC?Itís the green bus seen above.

Figure 4 Close-up of the naming convention for the LCD display.

5.       We need to add the following I/O pins:

a.       LCD_E which is the LCD enable for software control of the LCD screen.

b.      LCD_RS which is the LCD screen RESET control for when the reset is selected for the microcontroller.

c.       LCD_RW is the control that also software to Read data or Write data to the LCD screen.Usually, there is no reading of the LDC screen but plenty of writing.Writing should happen when line is held low.

d.      LCD_data[7..0] is the 8-bit line used to write ASCII characters to this screen.Other controls such as clear screen and cursor position are software commands sent over these data lines. The indication is that the port is bi-directional so use the bidir pin.

6.       Two more control output pins need to be added: LCD_ON and LCD_BLON which are the manual controls for turning the LCD on and turning the LCD Back Light on.These outputs are connected outside of the SOPC and are either connected to input pins or wired directly to Vcc if the designer prefers no options for the user.

Figure 5 manual switches wired high.

7.       One thing Iíve noticed is the pin assignments missing.This means we can import the assignment from Lab4.Open up the Import Assignments wizard.

Figure 6 Click path to the Import Assignments wizard.

Figure 7 Switch to Lab 4 and select the *.qsf file.

Figure 8 The Final screen before importing the assignments: click OK.

8.       A few comments: the Categories button allows you to select types of pin assignment.Since our design is pretty much a run of the mill design, selecting All is okay.No changes needed to be made in the Advanced section.

9.       All that remains is making the assignments for the modification for the LCD.

Figure 9 Assignment from the DE2 User manual, Table 4.6 on page 54.

10.   This pretty much finishes adding the LCD to the Lab 4 design.

11.   Since we are using the on-chip memory its size should be increased to 20480 bytes or 20KB to allow for the complete Count Binary program to be stored in the on-chip memory.

12.   We also should add the input button_pio[3..0] to allow switches SW0 to SW3 to control the displays.At this point in the course this should be considered a trivial exercise for students.

 

Figure 10 The complete SOPC for the Count Binary program.

13.   The sys_clk_timer which is used for the HAL architecture should have the Custom option changed to Full Featured. The data outputs for the lcd_display should be bidirectional.

 

Figure 11 The complete hardware system with assignments for the Count Binary program..

Figure 12 The complete pin assignments for the hardware used in Count Binary.

 

14.   When you start Nios II the workspace should use the same folder that the Quartus II hardware is located in.

15.   One immediate results of this attempt at using the on-chip memory is an error from a call to fopen in the software.This was not a problem in any of our previous builds; however, this is a C++ function call.

16.   The problem could be resolved by enabling C++ and eliminating the small C library in the BSP properties.The resulting build using this technique reveals that the on-chip memory is now too small to hold the program by 40KB. Obviously, failure to fit on a chip is a more elementary problem than an undefined function call.

17.   The 20KB plus another 40KB would require an on-chip memory of 64KB. Return to Quartus II to fix the hardware by entering 65356 in the size for the on-chip memory then from the Nios II menu under System have Assign Base Addresses fix any over lapping memory locations.

18.   Generate the new Nios II processor and close out of the SOPC Builder.The change is automatically saved and modified for the current design.

19.   After attempting to compile the new design, we encounter a fundamental limit to the use of the on-chip memory in the Cyclone II chip.

Figure 13 We have reached a dead end with the on-chip memory.

20.   The solution to this problem is the use of off-chip memory of which the DE2 board offers three choice, SDRAM, SRAM, and Flash Memory.Weíre going to go with SDRAM for right now.

21.   Since we are in Quartus open the SOPC Build wizard and eliminate the on-chip memory.

22.   Add the SDRAM controller found under external memory interfaces as seen in Figure 14.

Figure 14 Add the SDRAM Controller

 

23.   In the wizard that appears, none of the preset SDRAM memory devices are used on the DE2 evaluation board so we have to write our own specifications which are elaborated in the documentation.Select Custom in the Preset pull down and change the data width to 16 bits.Leave the rest of the options unchanged as seen in Figure 15.

Figure 15 SDRAM wizard as modified for the DE2 board, page 1.

24.   On the second page you can leave all the default settings as they appear in Figure 16.

Figure 16 Leave page 2 set to the defaults.

25.   Notice that the memory size is over 8 MB which should handle the hardware and C++ program.

26.   Auto-assign the memory base addresses then modify the processors reset and exception vector to use the SDRAM memory.

Figure 17 Modify the Reset and Exception vectors

27.   Generate the processor next.Here is what the processor looks like at this point:

Figure 18 Processor status

28.   Placing this processor in the Quartus design is simplified by deleting the old processor and moving the pins off to the right making room for a larger design.Insert the new revised process into the design from the library and reconnect the old pins to their proper location.

29.   Figure 19 is what the design in Quartus II looks like before adding the SDRAM pins and after fixing the old pins; your design can look different depending on what order you entered the peripherals in the SOPC Builder.

Figure 19 Before adding the SDRAM pins.

30.   Here is the pin list of I/O that need to be added:

Output:

- SDRAM_ADDR[11..0]

- SDRAM_BA[1..0]

- SDRAM_CAS_N

- SDRAM_CKE

- SDRAN_CS_N

- SDRAM_DQM[1..0]

-SDRAM_RAS_N

-SDRAM_WE_N

 

Bidirectional:

-SDRAM_DATA[15..0]

 

31.   Here are the SDRAM addresses I/O pins for 12 bits from the DE2 User Manual followed by the 16 I/O pins used for the Data bits.

32.   The 16 bit wide data bits are listed above and below are the control signals. There have been some changes in the naming convention for the Banks Addresses and Data Mask (from individual bits to busses) but not the pins so place your pins wisely.

33.   Next is what the I/O pins look like when connected:

Figure 20 SDRAM control pins

34.   At this point the connections that control SDRAM for read/write operation are set; however there is no clock to actually run the SDRAM chip. In order to use SDRAM successfully, it must run off a clock that is 3 ns slower than master clock driving the processor. If SDRAM_CLK is not created or is connected to the same clock as the processor then NIOS will encounter run-time errors when accessing memory.

35.   A "slow clock" will be created to drive SDRAM. Click on Tools -> MegaWizardPlug-In Manager and click Next.

Figure 21 Located next to some familiar tools.

36.   Page 1 of the ten page wizard.

Figure 22 Default selection then click Next.

37.   Go to the next page of this wizard.

Figure 23 Default selection shown for page 2.

38.   We are going to install a Phase-Locked-Loop circuitry by clicking on I/O and selecting ALLPLL.

Figure 24 Selection and naming the file.

39.   For the name, enter sdram_pll as seen in Figure 24 then click Next.

40.   On the third page change the device to Cyclone II and the frequency of the inclk0 input to 50.000 MHz and click Next.

Figure 25 Just two changes on this page.

41.   On page 4 uncheck all the boxes.

Figure 26 Uncheck the options here.

42.   Make no changes on page 5 of the wizard.

Figure 27 Make no changes on this page.

43.   On page 6 change clock frequency to 50 MHz and clock phase shift to 3ns.

Figure 28 Setting the output frequency and phase.

44.   Click thru the remaining pages making no changes because they are for other output clocks and on the summary page, page 10, make sure Quartus II Symbol file is checked off then click Finished.

Figure 29 Check off the sdram_pll.bst file in order for the Quartus II symbol file to be generated.

45.   After the design is generated it needs to be added to the design.

Figure 30 Select Yes to add the IP to your design.

46.   Besides being added to the files in the Navigator, youíll find the design in the Library.

Figure 31 Add the PLL to your design.

47.   Next we see what the PLL design looks like when added to the top-level.The phase degrees, 54, are the portion of 360 degrees that 3 nanosecond occupy of the 20 nanosecond period.

Figure 32 Here is the PLL inserted into the top-level design.

48.   Next compile the design and add the pins for the SDRAM; below is the design when you finish.

 

Figure 33 Design completed with pin assignments.

49.   This ends the hardware portion of the design.Download the design to the board and start Nios II from the Tools menu of Quartus:

Figure 34 Convenient location for starting the Nios II software.

50.   In this design when we build the Board Support Package select Support C++ and uncheck reduced device drivers and Small C Library.

Figure 35 Using C++ due to the large memory available.

51.   Here is the screen shot showing memory is assigned to the SDRAM locations.

Figure 36 Software is seeing the SDRAM addresses.

52.   Overall, the software BSP was generated followed by the building the project which ran as Nios II hardware with no hiccups.

53.   After completing this lab, investigate the use of the button_pio and the use of the LCD backlight. Demonstrate the design for the instructor and capture essential screen shots. Add your comments; especially, why you think the design didnít work for you before the July 4th break.