Wentworth Institute of Technology

Department of Electrical Engineering and Technology

Elec 667 Advanced Programmable Logic

Lab 3 Nios II Hardware Tutorial

 

Part 1 Hardware

1.       Create a new project using the New Project Wizard.  On page 1 change the working directory to C:/altera/13.0/quartus/qdesigns using the browser search button, add a new folder to the qdesigns folder called Lab3 and then select that folder.  The name of the project can be Lab3.   The device family is Cyclone II

 

Figure 1 Setting up the project

Figure 2 Page 3 selects the Family, method of Target selection, and device.

2.       Add a top-level schematic design by clicking on File>>New.  Saved as using the default name, Lab3

Figure 3 Save as Lab3.bdf.  This will be the top-level design to the project.

3.       Figure 4 shows what is included so far in that design: a clock I/O pin input called CLOCK, a bus with output pin named LEDG[7..0], and a wire connected to the Vcc connection.   Add these I/O features to your schematic diagram. 

Figure 4 Pins I/O before the Qsys is build.

4.       This schematic diagram should be saved at this point.  This sets Lab3.bdf as the top level design.   The Qsys processor will be a part inserted into Lab3.bdf.  The clock input can be connected to the Cyclone II global clock after the Qsys is generated and compiled.   The output I/O can be assigned at that time also.

5.       At this point we will need to build the Qsys processor.  It is almost exactly like the Qsys we built for Lab 1 with some minor differences. 

Figure 5 Name the processor core Lab3_Qsys

6.       Because you need the practice, build it again with the following exceptions:

a.       The name for the Qsys has to be different from the project/top-level design.  So I named my Lab3_Qsys.

b.      The recommends memory size is 20 KBytes of memory.  I have found you can get away with 16 Kbytes if the Nios II processor you select is the economy version.  The actual bits to enter is 20*1024 = 20480.

c.       For this design we only need one bus, 8 bits wide, named led_pio.

d.      Because the on-chip memory has been moved from its location in Lab 1 (used auto-assign base addresses) setting the reset vector reference to Absolute cause a failure in Eclipse.  Change the reset vectors reference to the location for onchip_memory2_0.s1.

7.       As you design this Qsys, refer to the document Working with Qsys document to figure out and remember the modifications needed to be made with this design and how you made them.

Figure 6 Lab3_Qsys has been added to the library under project.

 

Figure 7 Tidy up the schematic.  Notice that the file for Lab3_Qsys needs to be added to the project files on the left.

8.       After installing the Qsys in the schematic tidy it up a bit and take a screen shot for your lab report.

9.       Notice that in Figure 7 in the Project Navigator, Files tab, that the file for the Qsys is not listed. 

Figure 8 Right click on Files to start the click path to add the Qsys file.

Figure 9 Select the Lab3_Qsys.qsys file from the workspace using the browse button then click Add

Figure 10 Lab3_Qsys has been added to the Files in both locations.

10.   Compile your project at this time to add pin assignments. Most warnings can be disregarded.

11.   The pin assignments can be found in the DE2 User Manual.  They are replicated here for your convenience.   Output bit zero, LEDG[0], is assigned to the like-named output pin.  They are being connected to the green LEDs with the least significant bit to the right.

Figure 11 Output pin assignments.

12.   The clock input is assigned to PIN_N2.   This information is also found in the DE2 User Manual.

13.   If you use the method for pin assignments called Pin Planner, heed the following advice:

a.       Use the upper left box labeled Groups

b.      You can not assign Group Node Names

c.       Expand the Group to work on individual pin assignments

d.      By adding [1] to the clock input, this solo pin will appear in the Groups location.

e.      These assignments will put the LSB on the right of the green LEDs on the DE2 Board

 

Figure 12  Using the Pin Planner to assign pins.

 

Figure 13 The schematic displays pin assignments in Quartus v13.

14.   The instruction from the tutorial recommends compiling the design at this time.  You should do so.  By having two compilations, you are incrementally checking your design.  No sense in assigning pins which is labor intensive if there is a problem with the processor.

Figure 14 Results of the final compilation.

15.   Download the lab3.sof file to the board with the  icon from the right found in the output folder.    

 

Part II Software

16.   At this point the Eclipse software is used to select the sample program.  Use the instructions from Lab 2 which we completed last week and are summarized here:

a.       Open Eclipse from Quartus main menu, Tools>>Nios II Software Build Tools for Eclipse.

b.      Assign the Workspace to the folder containing the Quartus files for the project (qdesign>Lab3).

Figure 15 View of the folder with all the folders in it for Lab3.

c.       When Eclipse opens click on File>>New>>Nios II Application and BSP from Template.

d.      The Lab3.sopcinfo file should be in the folder seen when you open Browse.

e.      Add a version to the project name: count_binary_0.

f.        Select Count Binary from the selections listed under Project Template.

 

 

Figure 16 Setting the project parameters.

 

17.   After the project makes the application files and the BSP packages; be sure and check that your desired C program is included in the navigation tree of the application.  If not, close out of Eclipse, delete the folder software that Eclipse added to the project folder and try again.  This is also the methodology that we use when we revise the hardware in order to get Eclipse to look at the new *.sopcinfo file that would be created when you compile a revised core.

Figure 17 Checking for the desired file.

 

18.   At this point we need to check some setting for the BSP.  

a.       Right-clicking on the folder Count_Binary_0_bsp in the Project Explorer panel and selecting Properties at the bottom of the selections.  

b.      When the Properties dialog box opens select Nios II BSP Properties from the navigation tree on the left side of the box. 

c.       Make the changes specified here so that the Nios II BSP Properties appear as seen in Figure 19 of this lab. 

                                                              i.      Uncheck Support C++

                                                            ii.      Check Small C library

                                                          iii.      Check Reduced device drivers

d.      Click Apply after you’ve made the changes so other problems will not become an issue.  

 

 

Figure 18 Changes made to Properties dialogue box.

19.    Click on the BSP Editor… button next.

Figure 19 Verify the two boxes are checked off in this location.  Setting>Common>Hal sees the same thing.

Figure 20 Check that Enabled is selected for the reduced drivers under Settings.

 

20.   We check the reduced device drivers and small C library options are set in several places.

 

Figure 21 Check that Enabled is selected for small C Library under Settings.

21.   Check that the C++ feature is turned off next.  Some of the features may not appear in the same order on your Eclipse version with Quartus v12 as seen in these images but the path is the same.

 

Figure 22 Turn off the C++ option in the Settings.

22.   Turn on the small drivers under the Drivers Tab.

 

Figure 23 Select enable_small_driver under the Drivers Tab.

23.   At this point click on Generate.  Usually it will generate in 2 seconds.

24.   Next right-click on the application in the Project Explorer panel to select:  Build Project. 

 

Figure 24 Locations of what to right click on and Build Project selection.

Figure 25 After the build, notice that Eclipse sees the count_binary_0.elf file (2nd line).

25.   If the project builds without errors, right-click on the application and select Run As>> Nios II Hardware.  Your DE2 board will light up after the program turns on.  Watch the comment area as it starts up.

 

Figure 26 When you right click on the application (the first folder in the Project Explorer)

Figure 27 Alternate Run As location off the main menu.

26.   Both locations for Run As have an optional selection used to view problems called Run Configurations.  Various issues can be check with the JTAG and System ID/Time stamp here.

 

Figure 28 Run Configuration open automatically when the program is run.

27.   The program count_binary_0  runs when the hardware is downloaded  to the DE2 board.  It displays the count in the console window and flashes the LEDs.  If you did not name the PIO component in Nios II processor the same as seen in the comment section of the count_binary.c  the LEDs will not turn on.

 

Figure 29 Nios II Console screen.

28.   As a modest demonstration of your programming skills, change the label and try to make the program count down.

29.   Next turn on Debug.

Figure 30 Turning on Debug

30.   Another dialogue box opens asking what you want to debug, choose Nios II Hardware.  You may have to run through a few permissions windows from your operating system but eventually the Debug screen will open.

 

Figure 31 Debug window.

31.   Press the pause button.    There are additional program control icons along this menu bar. 

32.   The Debug feature of C programming is quite useful for editing and modifying the program.  Every time you make a change you will have to go back to the main Eclipse window to rebuild (compile) the modified program then download the object file to the board.

 

Lab Report

33.   Include screen shots and histories of your errors with particular emphasis on what worked and what didn’t and how you cleared your problems.  This becomes a very valuable log for the next lab. 

34.   Final Comment: Usually when you write software for hardware, you have to learn the names of the registers so that the software can call the correct memory address.  This involves learning the alias used in the hardware letting the header file sort out the actual address.  In this lab, for the first time, you have to write the hardware using the naming convention found in the software.  It’s one of the major differences that make addressable and programmable hardware unique for modern development in the 21st century.  When code is ported from one hardware manufacturer to another, the user code has to be modified; now, knowing the registers the code calls, the hardware can be renamed making the code totally portable.