Wentworth Institute of Technology
Department of Electrical Engineering
Elec 667 Advanced Programmable Logic
Lab 1 Soft Processor Design
Student learn how to design a
soft processor for installation in a FPGA using Quartus II and the DE2 Evaluation
Board. These instructions allow students
to choose between Quartus II v9.1 using the SOPC Builder and Quartus II v13.0
using Qsys. These instruction assume the
students have already taken a course in Digital Logic using Quartus II v9.1
using the DE2 Evaluation Board.
- A project
with top-level design Lab1.bdf is created that you are going to add a
processor to. Start with
File>>New Project Wizard; File>>New>>select Block
diagram/Schematic File; add 2 input pins (Clk and pio_in[3..0]), one Vcc
connection (library>primitive>other), and one output pin
(pio_out[7..0]); then save the design naming it the same as the
project. The Navigator window will
update with this name.
Figure 1 Declaring a project and setting
up the I/O.
this point students using an older version of Quartus and SOPC Builder continue
with the instruction in this lab. Student using a new version of Quartus and
wanting to learn/use Qsys continue with instructions located here. When you complete the Qsys design return at
instruction 18 of this lab.
on the SOPC Builder under Tools.
The SOPC wizard is started by clicking on the Nios II processor and
then clicking on Add at the bottom.
Figure 2 Where the Nios II Processor
is location in version 9.1
new CPU wizard had a slightly different first page and six tabs. Pick the “f” design as Brendon did for
the same reasons on the first page.
Leave the Hardware Divide unchecked. Below that are two vectors setting that
are blank; Reset and Exception which we will come back to as the wizard
won’t let you enter anything in the fields until a memory module is
declared. Skip the include boxes
for MMU and MPU.
Figure 3 Opening screen of the CPU
- On the following pages accept the defaults. On page 5, check off the level 3
debugger. On the final page simply
click Finish. When the wizard
disappears the CPU is present in the design.
Figure 4 The CPU is the first
component added to the design.
- Memory is added next.
For the sake of simplicity we will only add On-Chip memory for this
Figure 5 Location for the on-chip
- This opens a two page wizard that allows you to do
some tweaking. Change the Total
memory size to 8 Kbytes for this project.
Figure 6 Memory wizard.
- Once finished, double-click on the cpu_0 component in
the listing to open the CPU wizard again.
Now pull down on the choices
for the vectors and select the default addresses now listed for the
Reset and Exception vectors. Notice
also in the Narrative section at the bottom of the wizard that the
warnings asking you to update the parameters for these vectors
Figure 7 Vector assignments.
- Brendon added a timer but for this simple example we
will skip adding a timer.
- Parallel I/O is added, one for inputs and another for
outputs. Both are adjustable for
varying bus widths. For this design
use 4 bit inputs and 8 bit outputs.
Figure 8 Location of I/O bus
Figure 9 Adding input and output
- Since it is helpful to have easily recognizable
design names, change the default names to pio_in and pio_out
by right clicking on the name of the bus in the component list. An options list appears that will allow
you to modify the name in the field text box.
- Added the
JTAG UART which is found under Interface Protocols>>Serial. Again accept the defaults in the wizard
Figure 10 Location of the JTAG UART
are several other types of communication protocols you could add as
needed. Because this is a soft microprocessor,
you have your choice and you design the microprocessor to fit you design
needs. So if your design has a
sensor that only has SPI mode of communication then you add just that
modular component, or Ethernet or whatever.
we add system identification. The
software is rather fussy about naming the system so that has to be changed
immediately to sysid.
Figure 11 Location of the System ID
complete processor for this design.
Figure 12 Our design's processor
- At this point you are ready to generate the
processor. Click on Next at the
bottom of the screen and then on the next screen, make use Simulation is
unchecked then click on the Generate button. This takes a little time because it’s a
huge VHDL file of over 3000 lines.
Wait for the Narrative to say: System generation was successful;
then click on EXIT. This will add
into the Library files of the design your CPU custom made by you for you.
processor inserted into the library so click on the icon to add it in.
Figure 13 Insert your custom processor
into the project.
- Next compile the design. That is the purple arrow in the main
menu of Quartus. If you get some
errors, read them carefully. They
can be minor errors such as busses naming protocol. If you’ve a lot of errors it is
sometimes easier to start over. You
haven’t done that much work. Have
your instructor look at the problem and they might be able to decipher
what went wrong.
- We’re not going to simulate the design at this time
so our first design doesn’t require that we have designated the I/O pins
but it will eventually.
- Quartus II v9.1 does require that you declare the I/O
for the system clock: clk_0.
Connect this input to PIN_N2 the global clock for the Cyclone
II. Connect Vcc (primitives>>others)
to the reset_n input. Failure to do
both will result in a processor that doesn’t turn on and gives System ID
errors when you try to download a C program to the chip.
design compiled and had 31 warnings.
At this point we can conclude this lab. Submit a screen design of your processor
and write up any errors you may have encountered and how you solved
Figure 14 Hardware portion of the
project is completed.